HBT169M thyristors description glass passivated, sensitive gate thyristors in a plastic envelope, intended for use in general purpose switching and phase control applications. these devices are intended to be interfaced directly to microcontrollers, logic integrated circuits and other low power gate trigger circuits. quick reference data symbol parameter max. unit v drm , v rrm repetitive peak off-state voltages 400 v i t(av) average on-state current 0.5 a i t(rms) rms on-state current 0.8 a i tsm non-repetitive peak on-state current 8 a pin configuration pin description 1gate 2 anode 3 cathode 13 2 symbol ak g limtiing values symbol parameter min. max. units v drm , v rrm repetitive peak off-state voltages - 400 v i t(av) average on-state current (half sine wave; t lead 83 c) -0.5a i t(rms) rms on-state current (all conduction angles) - 0.8 a non-repetitive peak on-state current (t=10ms) - 8 a i tsm non-repetitive peak on-state current (t=8.3ms) - 9 a i 2 ti 2 t for fusing (t=10ms) - 0.32 a 2 s di t /dt repetitive rate of rise of on-state current after triggering (i tm =2a; i g =10ma; di g /dt=100ma/us) -50a/us i gm peak gate current - 1 a v gm peak gate voltage - 5 v v rgm peak reverse gate voltage 5 v p gm peak gate power - 2 w p g(av) average gate power (over any 20ms period) - 0.1 w tstg storage temperature - 150 c tj operating junction temperature - 125 c sot-89 www.kersemi.com
thermal resistances symbol parameter conditions min. typ. max. unit rth j-lead thermal resistance junction to lead rth j-a thermal resistance junction to ambient pcb mounted; lead length=4mm - - - 150 60 - k/w k/w static characteristics (ta=25 c) symbol parameter conditions min. typ. max. unit i gt gate trigger current v d =12v, i t =10ma gate open circuit - 50 200 ua i l latching current v d =12v, i gt =0.5ma; r gk =1k ? -26ma i h holding current v d =12v, i gt =0.5ma; r gk =1k ? -25ma v t on-state voltage i t =1a - 1.2 1.35 v v d =12v, i t =10ma gate open circuit -0.50.8v v gt gate trigger voltage v d = v drm(max) , i t =10ma; tj=125 c gate open circuit 0.2 0.2 - v i d ,i r off-state leakage current v d =v drm(max) ; v r = v rrm(max) ; tj=125 c; r gk =1k ? - 0.05 0.1 ma static characteristics symbol parameter conditions min. typ. max. unit dv d /dt critical rate of rise of off-state voltage v dm =67% v drm(max) ; tj=125 c exponential waveform; r gk =1k ? 500 800 - v/us tgt gate controlled turn-on time i tm =2a; v d =v drm(max) i g =10ma; di g /dt=0.1a/us -2-us tq circuit commutated turn-off time v d =67% v drm(max) ; tj=125 c i tm =1.6a; v r =35v; di tm /dt=30a/us dv d /dt=2v/us; r gk =1k ? - 100 - us www.kersemi.com
characteristics curve normalised gate trigger current igt(ta)/igt(25 o c), versus air temperature ta 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -25 25 75 125 175 ta( o c) igt/igt(25 o c) typical & maximum on-state characteristic 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 vt/v it/a typ 25oc 125oc normalised gate trigger voltage vgt(ta)/vgt(25 o c), versus air temperature ta 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 ta( o c) vgt/vgt(25 o c) normalised latching current il(ta)/il(25 o c), vrsus air temperature ta 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 -25 0 25 50 75 100 125 150 ta( o c) il/il(25 o c) maximum on-atate dissipation, ptot versus average on-state current, it(av) a=conduction angle 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0.2 0.4 0.6 0.8 1.0 if (a v )/a ptot/w a=90o a=120o a=180o normalised holding current ih(ta)/ih(25 o c), versus air temperature ta 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 140 ta/( o c) ih/ih(25 o c) www.kersemi.com
sot-89 dimension *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1732 0.1811 4.40 4.60 f 0.0583 0.0598 1.48 1.52 b 0.1594 0.1673 4.05 4.25 g 0.1165 0.1197 2.96 3.04 c 0.0591 0.0663 1.50 1.70 h 0.0551 0.0630 1.40 1.60 d 0.0945 0.1024 2.40 2.60 i 0.0138 0.0161 0.35 0.41 e 0.0141 0.0201 0.36 0.51 notes: 1.dimension and tolerance based on our spec. dated may. 05,1996. 2.controlling dimension: millimeters. 3.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 4.if there is any question with packing s pecification or packing method, please c ontact your local hsmc sales office. material: ? lead: 42 alloy ; solder plating ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of hsmc. ? hsmc reserves the right to make changes to its products without notice. ? hsmc semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? hsmc assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance. head office and factory: ? head office (hi-sincerity microelectronics corp.): 10f.,no. 61, sec. 2, chung-shan n. rd. taipei taiwan r.o.c. tel: 886-2-25212056 fax: 886-2-25632712, 25368454 ? factory 1: no. 38, kuang fu s. rd., fu-kou hsin-chu industrial park hsin-chu taiwan. r.o.c tel: 886-3-5983621~5 fax: 886-3-5982931 3 2 1 a b c d e f g h i style: pin 1.gate 2.anode 3.cathode marking: date code 1 hm 69 laser marking 3-lead sot-89 plastic surface mounted package hsmc package code: m www.kersemi.com
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